Electronic devices may be formed on thin-film silicon-on-insulator (SOI) substrates with reduced short channel effects, reduced parasitic and nodal capacitances, increased radiation hardness, reduced susceptibility to parasitic thyristor latch-up and reduced process complexity compared to bulk semiconductor devices. However, SOI devices may have parasitic contact resistances, such as high source and drain contact resistances to SOI MOSFETs.
One attempt to form an SOI MOSFET according to the prior art is disclosed in FIGS. 1A-1D. In particular, to form the structure of FIG. 1A, a buried oxide layer 12 and a silicon layer 14 thereon are formed using a conventional separation by implantation of oxygen (SIMOX) technique which involves implanting oxygen ions into a face of a silicon substrate 10. Then, a pad oxide layer 16, nitride layer 18 and photosensitive patterning layer 20 are sequentially formed. The nitride layer 18 is then patterned to define an active region in the silicon layer 14 using the photosensitive layer 20 as a mask. Field oxide isolation regions 22 are then formed by performing a relatively long and high temperature oxidation of the silicon layer 14 until the silicon layer 14 is consumed, using the patterned nitride layer 18 as a mask, as illustrated by FIG. 1B. The nitride layer 18 is then removed and impurity ions are-implanted into the silicon layer 14 to set the threshold voltage. An insulated gate electrode comprising a gate insulating layer 26, polycrystalline silicon and tungsten silicide (WSi.sub.x) gate electrode 28 and oxide spacers 30, is then formed on the silicon layer 14. The gate electrode 28 is then used as a mask to form the source region 14a and drain region 14b in the silicon layer 14, as illustrated by FIG. 1C. Conventional steps are then used to deposit an insulating layer 32 and then reflowing boro-silicate glass (BPSG) on the insulating layer 32 to form a planarized layer 34. The planarized layer 34 and insulating layer 32 are then etched to form source and drain contact holes. Source and drain electrodes 36 and 38 are then formed by patterning metallization on the planarized layer 34, as illustrated by FIG. 1D.
Unfortunately, the use of thin-film SOI substrates typically causes an increase in the sheet resistances of the source and drain regions of FETs formed therein and this increase typically causes a decrease in on-state current (I.sub.ds). These difficulties in using thin-films are more fully disclosed in an article by L. Su et al. entitled Optimization of Series Resistance in Sub-0.2 .mu.m SOI MOSFETs, International Electron Devices Meeting, No. 30.1.1-30.1.4, pp. 723-726. However, the use of thick-film SOI substrates is also problematic because high junction capacitances with the channel region typically result and because sub-threshold leakage current typically increases with the thickness of the silicon film.
Thus, notwithstanding prior art attempts to form SOI substrates and devices, there still continues to be a need for improved methods of forming SOI substrates and devices so that devices formed therein derive the above described benefits of SOI isolation, but do not suffer from high sheet resistances and high junction capacitances associated with thin-film devices.